library verilog;
use verilog.vl_types.all;
entity pmi_add_unsign is
    generic(
        pmi_data_width  : integer := 8;
        pmi_result_width: integer := 8
    );
    port(
        DataA           : in     vl_logic_vector;
        DataB           : in     vl_logic_vector;
        Cin             : in     vl_logic;
        Result          : out    vl_logic_vector;
        Cout            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_data_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_result_width : constant is 1;
end pmi_add_unsign;
